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 FST3125 -- 4-Bit Bus Switch
March 2008
FST3125 -- 4-Bit Bus Switch
Features
4 Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low ICC Zero Bounce in Flow-through Mode Control Inputs Compatible with TTL Level
Description
Fairchild switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The device is organized as four one1-bit switches with separate /OE inputs. When /OE is LOW, the switch is ON and port A is connected to port B. When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports.
Ordering Information
Part Number
FST3125M FST3125MX FST3125QSC FST3125QSCX FST3125MTC FST3125MTCX
Operating Temperature Range
-40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C -40 to 85C
Package
14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch Narrow 14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch Narrow 16-Lead, Quarter Size Outline Package (QSOP) MO-137 0.150 inch Wide 16-Lead, Quarter Size Outline Package (QSOP) MO-137 0.150 inch Wide 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide
Packing Method
Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard. The Fairchild switch family derives from and embodies Fairchild's proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.
Figure 1. Logic Diagram
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3 www.fairchildsemi.com
FST3125 -- 4-Bit Bus Switch
Pin Configurations
/OE1 1A
1
14
VCC /OE4 4A
NC
1
16
VCC /OE4 4A
2
13
/OE1 1A
2
15
3
14
1B
3
12
1B
4
13
4B
/OE2 2A
4
11
4B
/OE2 5 12 /OE3 3A
5
10
/OE3
2A 6 11
2B
6
9
3A
2B 7 10 3B
GND
7
8
3B
GND 8 9 NC
Figure 2. SOIC and TSSOP Pin Assignments
Figure 3. QSOP Pin Assignments
Pin Descriptions
Pin Names
/OE1, /OE2, /OE3, /OE4 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B NC VCC GND
Description
Bus Switch Enables Bus A Bus B Not Connected Supply Voltage Ground
Truth Table
Inputs
/OE LOW HIGH
Inputs/Outputs
A, B A=B High Impedance
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 2
FST3125 -- 4-Bit Bus Switch
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC VS VIN IIK IOUT ICC / IGND TSTG Supply Voltage DC Switch Voltage DC Input Voltage DC Input Current
(1)
Parameter
Min.
-0.5 -0.5 -0.5
Max.
7.0 7.0 7.0 -50 128 100
Unit
V V V mA mA mA C
DC Output Sink Current DC VCC / GND Current Storage Temperature Range -65
+150
Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC VIN VOUT tr , tf TA Input Voltage Output Voltage
Parameter
Power Supply Operating
Min.
4.0 0 0
Max.
5.5 5.5 5.5 5 DC +85
Unit
V V V ns/V C
Input Rise and Fall Time
Switch Control Input Switch I/O
(2)
0 0 -40
Operating Temperature, Free Air
Note: 2. Unused control inputs must be held HIGH or LOW. They may not float.
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 3
FST3125 -- 4-Bit Bus Switch
DC Electrical Characteristics
Typical values are at VCC = 5.0V and TA = 25C.
Symbol
VIK VIH VIL IIN IOZ
Parameter
Clamp Diode Voltage High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Off-state Leakage Current
Conditions
IIN = -18mA
VCC (V)
4.5 4.0 to 5.5 4.0 to 5.5
TA=-40 to +85C Min.
2.0 0.8 1.0 1.0 4 4 8 11 7 7 15 20 3 2.5
Units
V V V A A
Typ.
Max.
-1.2
0 VIN 5.5 0 A, B VCC VIN = 0V, IIN = 64mA
5.5 5.5 4.5 4.5 4.5 4.0 5.5 5.5
RON
Switch On Resistance
(3)
VIN = 0V, IIN = 30mA VIN = 2.4V, IIN = 15mA VIN = 2.4V, IIN = 15mA VIN = VCC or GND, IOUT = 0 One Input at 3.4V, Other Inputs at VCC or GND
ICC ICC
Quiescent Supply Current Increase in ICC per Input
A mA
Note: 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the A or B pins.
AC Electrical Characteristics
TA = -40 to +85C, CL = 50pF, and RU = RD = 500.
Symbol
tPHL, tPLH
Parameter
Propagation Delay (4) Bus-to-Bus Output Enable Time
Conditions
VIN = Open VIN = 7V for tPZL VIN = Open for tPZH VIN = 7V for tPLZ VIN = Open for tPHZ
VCC = 4.5 - 5.5V Min. Max.
0.25
VCC = 4.0V Min. Max.
0.25
Units
ns
Figure
Figure 4 Figure 5 Figure 4 Figure 5 Figure 4 Figure 5
tPZH ,tPZL
1.0
5.0
5.5
ns
tPHZ, tPLZ
Output Disable Time
1.5
5.3
5.6
ns
Note: 4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by an ideal voltage source (zero output impedance).
Capacitance
TA = +25C, f = 1MHz. Capacitance is characterized, but not tested.
Symbol
CIN CI/O
Parameter
Control Pin Input Capacitance Input/Output Capacitance
Conditions
VCC = 5.0V VCC, /OE = 5.0V
Typ.
3 2
Units
pF pF
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 4
FST3125 -- 4-Bit Bus Switch
AC Loadings and Waveforms
Notes: Input driven by 50 source terminated in 50. CL includes load and stray capacitance. Input PRR = 1.0MHz, tw = 500ns. Figure 4. AC Test Circuit
Figure 5. AC Waveforms
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 5
FST3125 -- 4-Bit Bus Switch
Physical Dimensions
8.75 8.50 7.62
14 8
A
0.65
B
5.60 6.00 4.00 3.80
PIN ONE INDICATOR
1
7
1.70
1.27
1.27 (0.33)
0.51 0.35
0.25
M
LAND PATTERN RECOMMENDATION
CBA
1.75 MAX 1.50 1.25 0.25 0.10
C 0.10 C
SEE DETAIL A
0.25 0.19
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13
0.50 X 45 0.25 R0.10 R0.10
8 0
0.90 0.50 (1.04)
DETAIL A
SCALE: 20:1
SEATING PLANE
Figure 6. 14-Lead, Small-Outline Integrated Circuit (SOIC) 0.150-inch Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 6
FST3125 -- 4-Bit Bus Switch
Physical Dimensions
TOP VIEW
LAND PATTERN RECOMMENDATION
SIDE VIEW
END VIEW
DETAIL A
Figure 7. 16-Lead, Quarter-Size Outline Package (QSOP), MO-1370.150-inch Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 7
FST3125 -- 4-Bit Bus Switch
Physical Dimensions
0.43 TYP
0.65
1.65
0.45
6.10
12.00TOP R0.09 min
& BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 8. 14-Lead, Thin Shrink Small Outline Package (TSSOP) MO-153, 4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 8
FST3125 -- 4-Bit Bus Switch
(c) 2005 Fairchild Semiconductor Corporation FST3125 * Rev. 1.0.3
www.fairchildsemi.com 9


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